The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, the present invention relates to a technique for efficient logic power gating with data retention for IC devices that have xe2x80x9cactivexe2x80x9d and xe2x80x9cstandbyxe2x80x9d modes of operation.
Power gating peripheral logic blocks for IC memory devices are known. To date, attempts to reduce the leakage current for these circuits have exhibited two significant problems. First, even with extra power gating, the leakage current is still unacceptably high. Secondly, the state of the logic devices, latches, flip-flops, registers and the like is lost during the xe2x80x9cstandbyxe2x80x9d, or power-gated, mode.
U.S. Pat. No. 5,973,552 attempts to address the former problem by raising the gate voltage of the power gating devices to a boosted voltage level. This is effective in reducing the undesired current leakage (subthreshold current) of these devices but is a cumbersome process. The specification of this particular patent further describes a means for effectuating this end that minimizes the charge consumed out of the Vbb or Vpp supplies through the addition of more circuitry.
As to the latter problem, an article entitled xe2x80x9cA Novell Powering-down Scheme for Low Vt CMOS Circuitsxe2x80x9d published in the 1998 Symposium on VLSI Circuits Digest of Technical Papers by Kumagai et al. outlines a way to maintain the logic states of power-gated logic that fails to work for low voltage complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) circuits. As described, the article particularly illustrates the use of PN diodes to clamp the internal power supplies to within a diode drop of the external power supplies. While this approach may be acceptable with respect to circuits which operate in the range of 1.5 volts, it fails to function for ultra low voltage designs in the range of 0.8 volts or lower.
Another article by Yamagata et al., xe2x80x9cCircuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMsxe2x80x9d published in the 1995 IEEE International Solid-State Circuits Conference (ISSCC) at pp. 248-249 illustrates logic transistor bodies tied to external supplies for different reasons such as the speed of entering and leaving a standby mode and not for the purpose of reducing current leakage in a standby mode.
The technique for efficient logic power gating with data retention for IC devices that have xe2x80x9cactivexe2x80x9d and xe2x80x9cstandbyxe2x80x9d modes of operation in accordance with the present invention disclosed herein overcomes both of the aforementioned problems encountered in conventional approaches.
By way of background, the threshold voltage (xe2x80x9cVtxe2x80x9d)of a metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) transistor is known to be affected by the voltage which is applied to the back contact, or xe2x80x9cback gatexe2x80x9d. The voltage difference between the source and the bulk (xe2x80x9cVBSxe2x80x9d) changes the width of the depletion layer and, therefore, also the voltage across the oxide due to the change of the charge in the depletion region. This is known as the xe2x80x9cbody effectxe2x80x9d, or substrate bias effect, and stated another way, it is the variation of the threshold voltage of an MOS transistor due to a variation of the substrate or bulk voltage to the back contact.
In accordance with the technique of the present invention, the first mentioned problem inherent in prior approaches is solved using external voltage supplies (xe2x80x9cVCCEXTxe2x80x9d and xe2x80x9cVSSEXTxe2x80x9d) , wherein the Vt of the MOS devices is unaltered during xe2x80x9cactivexe2x80x9d modes of operation when VCCext=VCCint and VSSext=VSSint (where xe2x80x9cVCCINTxe2x80x9d and xe2x80x9cVSSINTxe2x80x9d are the voltages on internal supply nodes) but the Vt will rise, reducing leakage, during xe2x80x9cstandbyxe2x80x9d mode when VCCint and VSSint drift towards each other due to the increased body effect. This constitutes, in essence, a positive feedback effect wherein, the more the logic devices leak, the more the internal voltage supplies will collapse, which increases the back gate voltage.
The latter identified problem of conventional designs is then overcome by using additional upper and lower MOS transistors nodes instead of PN diodes for coupling the external voltage supplies to the internal voltage. These additional devices serve to clamp the internal voltages to a level that will maintain the data in the logic circuits, since the Vt of the transistors can be made to be much less than 0.7 volts, the built in voltage of a diode.
Particularly disclosed herein is an integrated circuit logic device having supply and reference voltage input lines thereof. The integrated circuit device comprises an internal supply voltage node which is selectively couplable to the supply voltage line in response to an input signal supplied to a gate terminal of a first MOS transistor. An internal reference voltage node is also selectively couplable to the reference voltage line in response to a complement of the input signal supplied to a gate terminal of a second MOS transistor. A third MOS transistor is coupled in parallel with the first MOS transistor between the supply voltage line and the internal supply voltage node and has a gate terminal coupled to the supply voltage line and a back gate coupled to the internal supply voltage node. A fourth MOS transistor is coupled in parallel with the second MOS transistor between the reference voltage line and the internal reference voltage node and has a gate terminal coupled to the reference voltage line and a back gate coupled to the internal reference voltage node. A logic circuit comprising a plurality of logic gates is coupled between the internal supply voltage node and the internal reference voltage node.
Also disclosed herein is an integrated circuit device comprising a plurality of logic gates coupled between an internal supply voltage node and an internal reference voltage node. First and second parallel coupled MOS transistors couple a supply voltage line to the internal supply voltage node and third and fourth parallel coupled MOS transistors couple a reference voltage line to the internal reference voltage node. First and second complementary input lines are respectively coupled to gate terminals of the first and third MOS transistors while gate terminals of the second and fourth MOS transistors are coupled to the supply voltage line and the reference voltage line respectively.